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1 of 34 rev: 122203 general description the DS26401DK is an easy-to-use evaluation board for the ds26401 octal t1/e1/j1 framer. it is intended to be used as a daughter card with the dk101 motherboard or the dk2000 motherboard. the DS26401DK comes complete with a ds26401 octal framer, two ds21448 quad lius, transformers, termination resistors, network connectors, and motherboard connectors. the dk101/dk2000 motherboard and the dallas? chipview software give point-and-click access to configurations and status registers from a windows -based pc. on-board leds indicate loss-of-signal, loss-of-frame, and interrupt status. each DS26401DK is shipped with a free dk101 motherboard. for complex applications, the dk2000 high-performance demo kit motherboard can be purchased separately. windows is a registered trademark of microsoft corp. design kit contents DS26401DK board dk101 low-cost motherboard cd-rom chipview software DS26401DK data sheet dk101 data sheet ds26401 data sheet ds21448 data sheet ds26401 errata sheet ds21448 errata sheet features demonstrates key functions of the ds26401 octal t1/e1/j1 framer includes two ds21448 quad lius, transformers, bnc and rj45 connectors, and termination passives compatible with dk101 and dk2000 demo kit motherboards dk101/dk2000 and chipview software provide point-and-click access to the ds26401 register set all equipment-side framer pins are easily accessible for external data source/sink memory-mapped fpga provides flexible clock/data/sync connections among framer ports and dk2000 motherboard leds for loss-of-signal, loss-of-frame, and interrupt easy-to-read silk-screen labels identify the signals associated with all connectors, jumpers, and leds ordering information part description DS26401DK ds26401 demo kit daughter card (with included dk101 motherboard) DS26401DK octal t1/e1/j1 framer design kit daughter card www.maxim-ic.com
DS26401DK octal t1/e1/j1 framer design kit 2 of 34 component list designation qty description supplier part c1, c3, c5, c7, c9, c11, c13, c15, c17?c24, c26, c28?c31, c35?c42 29 00.1 f 20%, 16v x7r ceramic capacitors (0603) avx 0603yc104mat c2, c4, c6, c8, c10, c12, c14, c16 8 1 f 10%, 16v ceramic capacitors (1206) panasonic ecj-3yb1c105k ds1, ds18 2 led, green, smd panasonic ln1351c ds2?ds17 16 led, red, smd panasonic ln1251c j1, j3?j10, j12-j18 16 5-pin connectors, 75 bnc vertical bourns cp-bncpc-004 j2, j11 2 right-angle, rj45 8-pin 4-port jack 3m electronics 43223-8140 j19, j20 2 50-pin headers, socket, smd dual row, vertical samtec tfm-125-02-s-d-lc j21, j23, j25, j27, j29, j31, j33, j35 8 20-pin headers, dual row, vertical samtec hdr-tsw-110-14-t-d j22, j24, j26, j28, j30, j32, j34, j36 8 10-pin headers, dual row, vertical murrietta n/a jp1 1 12-pin connector, dual row, vertical murrietta n/a r1, r2, r5, r6, r9, r10, r13, r14, r17, r18, r21, r22, r25, r26, r29, r30, r67 17 0 1%, 1/16w resistors (0603) avx cj10-000f r3, r4, r7, r8, r11, r12, r15, r16, r19, r20, r23, r24, r27, r28, r31, r32 16 60.4 1%, 1/16w resistors (0603) panasonic erj-3ekf60r4v r33?r35 3 10k 5%, 1/16w resistors (0603) panasonic erj-3geyj103v r36, r37, r68 3 330 5%, 1/16w resistors (0603) panasonic erj-3geyj331v r38, r59?r66 9 30.1 1%, 1/16w resistors (0603) panasonic erj-3ekf30r1v r39?r54 16 300 5%, 1/16w resistors (0603) panasonic erj-3geyj301v r55?r58 4 10.0k 1%, 1/16w resistors (0603) panasonic erj-3ekf1002v t1?t8 8 xfmr, dual, 16-pin smt pulse engineering tx1467 u1 1 octal t1/e1/j1 framer dallas semiconductor ds26401 u2, u3 2 3.3v e1/t1/j1 quad liu 128-pin lqfp, 0c to +70c dallas semiconductor ds21448l u4 1 1m prom for fpga 44-pin tqfp xilinx xc18v01vq44c_u u6 1 8-pin max/so 2.5v or adj maxim max1792eua25 u7 1 xilinx spartan 2.5v fpga, 256-pin bga xilinx xc2s50-5fg256c
DS26401DK octal t1/e1/j1 framer design kit 3 of 34 board floorplan port 2 rj45 port 8 rj45 port 1 rj45 port 3 rj45 port 4 rj45 port 6 rj45 port 5 rj45 port 7 rj45 ds21448 liu ds26401 framer fpga cpu interface cpu interface test points (x4) tclk tsysclk tsync tssync tsig tser tchblk tclko rclk rsysclk rsync rmsync rsig rser rchblk jtag i/f led rlof, rlos x 4 port 2 bnc port 8 bnc port 1 bnc port 3 bnc port 4 bnc port 6 bnc port 5 bnc port 7 bnc xfmr txrx xfmr txrx xfmr txrx xfmr txrx xfmr txrx xfmr txrx xfmr txrx xfmr txrx ds21448 liu led rlof, rlos x 4 config prom test points (x4) tclk tsysclk tsync tssync tsig tser tchblk tclko rclk rsysclk rsync rmsync rsig rser rchblk
DS26401DK octal t1/e1/j1 framer design kit 4 of 34 quick setup (register view) connect DS26401DK to dk101 motherboard. connect serial cable to a pc and dk101. power dk101 with 3.3v. load chipview software. select com port. select register view. for t1 applications, load the 401_global_t1_ds26401dc.def file. for e1 applications, load the 401_global_e1_ds26401dc.def file. make sure that all the register settings are correct for the proper function desired for the DS26401DK. please refer to the ds26401 data sheet ( www.maxim-ic.com/ds26401 ) and the ds21448 data sheet ( www.maxim-ic.com/ds21448 ) for all questions pertaining to device functionality . address map dk101 daughter card address space begins at 0x81000000. dk2000 daughter card address space begins at: 0x30000000 for slot 0 0x40000000 for slot 1 0x50000000 for slot 2 0x60000000 for slot 3 all offsets given below are relative to the beginning of the daughter card address space. table 1. daughter card address map offset span number ds26401 ds21448 fpga 1 0x1000 0x2000 0x10 2 0x1200 0x3000 0x20 3 0x1400 0x4000 0x30 4 0x1600 0x5000 0x40 5 0x1800 0x6000 0x50 6 0x1a00 0x7000 0x60 7 0x1c00 0x8000 0x70 8 0x1e00 0x9000 0x80 registers in the fpga can be easily modified using chipview.exe host-based user-interface software along with the definition file named ds26401dc_fpga.def .
DS26401DK octal t1/e1/j1 framer design kit 5 of 34 fpga register map table 2. fpga register map offset name type description 0x0000 bid read-only board id 0x0002 xbidh read-only high nibble extended board id 0x0003 xbidm read-only middle nibble extended board id 0x0004 xbidl read-only low nibble extended board id 0x0005 brev read-only board fab revision 0x0006 arev read-only board assembly revision 0x0007 prev read-only pld revision 0x0010 0x0020 0x0030 0x0040 0x0050 0x0060 0x0070 0x0080 tsig_sr ?1 tsig_sr ?2 tsig_sr ?3 tsig_sr ?4 tsig_sr ?5 tsig_sr ?6 tsig_sr ?7 tsig_sr ?8 control ds26401 tsig pin setting port 1 ds26401 tsig pin setting port 2 ds26401 tsig pin setting port 3 ds26401 tsig pin setting port 4 ds26401 tsig pin setting port 5 ds26401 tsig pin setting port 6 ds26401 tsig pin setting port 7 ds26401 tsig pin setting port 8 0x0011 0x0021 0x0031 0x0041 0x0051 0x0061 0x0071 0x0081 tser_sr ?1 tser_sr ?2 tser_sr ?3 tser_sr ?4 tser_sr ?5 tser_sr ?6 tser_sr ?7 tser_sr ?8 control ds26401 tser pin setting port 1 ds26401 tser pin setting port 2 ds26401 tser pin setting port 3 ds26401 tser pin setting port 4 ds26401 tser pin setting port 5 ds26401 tser pin setting port 6 ds26401 tser pin setting port 7 ds26401 tser pin setting port 8 0x0012 0x0022 0x0032 0x0042 0x0052 0x0062 0x0072 0x0082 tssync_sr ?1 tssync_sr ?2 tssync_sr ?3 tssync_sr ?4 tssync_sr ?5 tssync_sr ?6 tssync_sr ?7 tssync_sr ?8 control ds26401 tssync source port 1 ds26401 tssync source port 2 ds26401 tssync source port 3 ds26401 tssync source port 4 ds26401 tssync source port 5 ds26401 tssync source port 6 ds26401 tssync source port 7 ds26401 tssync source port 8 0x0013 0x0023 0x0033 0x0043 0x0053 0x0063 0x0073 0x0083 tsysclk ?1 tsysclk ?2 tsysclk ?3 tsysclk ?4 tsysclk ?5 tsysclk ?6 tsysclk ?7 tsysclk ?8 control ds26401 tsysclk source port 1 ds26401 tsysclk source port 2 ds26401 tsysclk source port 3 ds26401 tsysclk source port 4 ds26401 tsysclk source port 5 ds26401 tsysclk source port 6 ds26401 tsysclk source port 7 ds26401 tsysclk source port 8 0x0014 0x0024 0x0034 0x0044 0x0054 0x0064 0x0074 0x0084 rsysclk ?1 rsysclk ?2 rsysclk ?3 rsysclk ?4 rsysclk ?5 rsysclk ?6 rsysclk ?7 rsysclk ?8 control ds26401 rsysclk source port 1 ds26401 rsysclk source port 2 ds26401 rsysclk source port 3 ds26401 rsysclk source port 4 ds26401 rsysclk source port 5 ds26401 rsysclk source port 6 ds26401 rsysclk source port 7 ds26401 rsysclk source port 8
DS26401DK octal t1/e1/j1 framer design kit 6 of 34 table 2. register map (continued) offset name type description 0x0015 0x0025 0x0035 0x0045 0x0055 0x0065 0x0075 0x0085 tclk ?1 tclk ?2 tclk ?3 tclk ?4 tclk ?5 tclk ?6 tclk ?7 tclk ?8 control ds26401tclk source port 1 ds26401tclk source port 2 ds26401tclk source port 3 ds26401tclk source port 4 ds26401tclk source port 5 ds26401tclk source port 6 ds26401tclk source port 7 ds26401tclk source port 8 0x0016 0x0026 0x0036 0x0046 0x0056 0x0066 0x0076 0x0086 rsync ?1 rsync ?2 rsync ?3 rsync ?4 rsync ?5 rsync ?6 rsync ?7 rsync ?8 control ds26401rsync source port 1 ds26401rsync source port 2 ds26401rsync source port 3 ds26401rsync source port 4 ds26401rsync source port 5 ds26401rsync source port 6 ds26401rsync source port 7 ds26401rsync source port 8 0x0017 0x0027 0x0037 0x0047 0x0057 0x0067 0x0077 0x0087 tsync ?1 tsync ?2 tsync ?3 tsync ?4 tsync ?5 tsync ?6 tsync ?7 tsync ?8 control ds26401tsync source port 1 ds26401tsync source port 2 ds26401tsync source port 3 ds26401tsync source port 4 ds26401tsync source port 5 ds26401tsync source port 6 ds26401tsync source port 7 ds26401tsync source port 8 0x0090 clk control liu mclk and ref clk source id registers bid: board id (offset = 0x0000) bid is read-only with a value of 0xd. xbidh: high nibble extended board id (offset = 0x0002) xbidh is read-only with a value of 0x0. xbidm: middle nibble extended board id (offset = 0x0003) xbidm is read-only with a value of 0x1. xbidl: low nibble extended board id (offset = 0x0004) xbidl is read-only with a value of 0x6. brev: board fab revisi on (offset = 0x0005) brev is read-only and displays the current fab revision. arev: board assembly revision (offset = 0x0006) arev is read-only and displays the current assembly revision. prev: pld revision (offset = 0x0007) prev is read-only and displays the current pld firmware revision.
DS26401DK octal t1/e1/j1 framer design kit 7 of 34 control registers register name: tsig_sr register description: ds26401 tsig x pin setting register offset: 0x0010, 0x0020, 0x0030, 0x0040, 0x0050, 0x0060, 0x0070, 0x0080 bit # 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 bit 0 to 7: ds26401 port x tsig source (d7, d6, d5, d4, d3, d2, d1, d0) the source for tser is defined as shown in table 3. table 3. tserx source definition d3, d2, d1, d0 tsig connection 0000 tri-state tsig 0001 drive tsig with rsig1 0010 drive tsig with rsig2 0011 drive tsig with rsig3 0100 drive tsig with rsig4 0101 drive tsig with rsig5 0110 drive tsig with rsig6 0111 drive tsig with rsig7 1000 drive tsig with rsig8 1010 drive tsig with t1 osc 1011 drive tsig with e1 osc 1100 drive tsig with 16.384mhz 1101 drive tsig with a logic 0 1110 drive tsig with a logic 1 1111 tri-state tsig note: initial values are such that all values are tri-stated.
DS26401DK octal t1/e1/j1 framer design kit 8 of 34 register name: tser_sr register description: ds26401 tserx pin setting register offset: 0x0011, 0x0021, 0x0031, 0x0041, 0x0051, 0x0061, 0x0071, 0x0081 bit # 7 6 5 4 3 2 1 0 name ? ? ? ? d3 d2 d1 d0 bit 0 to 3: ds26401 port x tser source (d3, d2, d1, d0) the source for tser is defined as shown in table 4. table 4. tserx source definition d3, d2, d1, d0 tser connection 0000 tri-state tser 0001 drive tser with rser1 0010 drive tser with rser2 0011 drive tser with rser3 0100 drive tser with rser4 0101 drive tser with rser5 0110 drive tser with rser6 0111 drive tser with rser7 1000 drive tser with rser8 1010 drive tser with t1 osc 1011 drive tser with e1 osc 1100 drive tser with 16.384mhz 1101 drive tser with a logic 0 1110 drive tser with a logic 1 1111 tri-state tser note: initial values are such that all ports are tri-stated.
DS26401DK octal t1/e1/j1 framer design kit 9 of 34 register name: tssync_sr register description: ds26401 tssyncx pin setting register offset: 0x0012, 0x0022, 0x0032, 0x0042, 0x0052, 0x0062, 0x0072, 0x0082 bit # 7 6 5 4 3 2 1 0 name ? ? ? ? d3 d2 d1 d0 default 0 0 0 0 0 1 0 1 bit 0 to 2: ds26401 port x tssync source (d3, d2, d1, d0) the source for tssync is defined as shown in table 5. table 5. tssyncx source definition d3, d2, d1, d0 tssync connection 0000 tri-state tssync 0001 drive tssync with rmsync1 0010 drive tssync with rmsync2 0011 drive tssync with rmsync3 0100 drive tssync with rmsync4 0101 drive tssync with rmsync5 0110 drive tssync with rmsync6 0111 drive tssync with rmsync7 1000 drive tssync with rmsync8 1010 drive tssync with t1 osc 1011 drive tssync with e1 osc 1100 drive tssync with 16.385mhz 1101 drive tssync with a logic 0 1110 drive tssync with a logic 1 1111 tri-state tssync note: initial values are such that all ports are tri-stated.
DS26401DK octal t1/e1/j1 framer design kit 10 of 34 register name: tsysclk_sr register description: ds26401 tsysclkx pin setting register offset: 0x0013, 0x0023, 0x0033, 0x0043, 0x0053, 0x0063, 0x0073, 0x0083 bit # 7 6 5 4 3 2 1 0 name ? ? ? ? d3 d2 d1 d0 bit 0 to 2: ds26401 port x tsysclkc source (d3, d2, d1, d0) the source for tsysclk is defined as shown in table 6. table 6. tsyclkx source definition d3, d2, d1, d0 tsysclk connection 0000 tri-state tsysclk 0001 drive tsysclk with rchblk 1 0010 drive tsysclk with rchblk 2 0011 drive tsysclk with rchblk 3 0100 drive tsysclk with rchblk 4 0101 drive tsysclk with rchblk 5 0110 drive tsysclk with rchblk 6 0111 drive tsysclk with rchblk 7 1000 drive tsysclk with rchblk 8 1001 bpclk 1010 drive tsysclk with t1 osc 1011 drive tsysclk with e1 osc 1100 drive tsysclk with 16.385mhz 1101 drive tsysclk with a logic 0 1110 drive tsysclk with a logic 1 1111 tri-state tsysclk note: initial values are such that all ports are tri-stated.
DS26401DK octal t1/e1/j1 framer design kit 11 of 34 register name: rsysclk_sr register description: ds26401 rsysclkx pin setting register offset: 0x0014, 0x0024, 0x0034, 0x0044, 0x0054, 0x0064, 0x0074, 0x0084 bit # 7 6 5 4 3 2 1 0 name ? ? ? ? d3 d2 d1 d0 bit 0 to 2: ds26401 port x rsysclkc source (d3, d2, d1, d0) the source for rsysclk is defined as shown in table 7. table 7. rsysclkx source definition d3, d2, d1, d0 rsysclk connection 0000 tri-state rsysclk 0001 drive rsysclk with tchblk 1 0010 drive rsysclk with tchblk 2 0011 drive rsysclk with tchblk 3 0100 drive rsysclk with tchblk 4 0101 drive rsysclk with tchblk 5 0110 drive rsysclk with tchblk 6 0111 drive rsysclk with tchblk 7 1000 drive rsysclk with tchblk 8 1001 bpclk 1010 drive rsysclk with t1 osc 1011 drive rsysclk with e1 osc 1100 drive rsysclk with 16.385mhz 1101 drive rsysclk with a logic 0 1110 drive rsysclk with a logic 1 1111 tri-state rsysclk note: initial values are such that all ports are tri-stated.
DS26401DK octal t1/e1/j1 framer design kit 12 of 34 register name: tclk_sr register description: ds26401 tclkx pin setting register offset: 0x0015, 0x0025, 0x0035, 0x0045, 0x0055, 0x0065, 0x0075, 0x0085 bit # 7 6 5 4 3 2 1 0 name ? ? ? ? d3 d2 d1 d0 bit 0 to 2: ds26401 port x tclk source (d3, d2, d1, d0) the source for tclk is defined as shown in table 8. table 8. tclkx source definition d3, d2, d1, d0 tclk connection 0000 tri-state tclk 0001 drive tclk with tclk 1 0010 drive tclk with tclk 2 0011 drive tclk with tclk 3 0100 drive tclk with tclk 4 0101 drive tclk with tclk 5 0110 drive tclk with tclk 6 0111 drive tclk with tclk 7 1000 drive tclk with tclk 8 1010 drive tclk with t1 osc 1011 drive tclk with e1 osc 1100 drive tclk with 16.385mhz 1101 drive tclk with a logic 0 1110 drive tclk with a logic 1 1111 tri-state tclk note: initial values are such that all ports are tri-stated. also note that rclk from the liu (ds21448) does not go directly to the fpga. however, it is routed to the ds26401 and a test he ader. to get rclk to fan out to all the ports on the ds26401, simply tri-state a port on the fpga and manually jumper the rclk x pin to the tclk x pin. then you can route that signal with register values 0001 to 1000 in the tclk_sr.
DS26401DK octal t1/e1/j1 framer design kit 13 of 34 register name: rsync_sr register description: ds26401 rsyncx pin setting register offset: 0x0016, 0x0026, 0x0036, 0x0046, 0x0056, 0x0066, 0x0076, 0x0086 bit # 7 6 5 4 3 2 1 0 name ? ? ? ? d3 d2 d1 d0 bit 0 to 2: ds26401 port x rsync source (d3, d2, d1, d0) the source for rsync is defined as shown in table 9. table 9. rsyncx source definition d3, d2, d1, d0 rsync connection 0000 tri-state rsync 0001 drive rsync with tsync 1 0010 drive rsync with tsync 2 0011 drive rsync with tsync 3 0100 drive rsync with tsync 4 0101 drive rsync with tsync 5 0110 drive rsync with tsync 6 0111 drive rsync with tsync 7 1000 drive rsync with tsync 8 1010 drive rsync with t1 osc 1011 drive rsync with e1 osc 1100 drive rsync with 16.385mhz 1101 drive rsync with a logic 0 1110 drive rsync with a logic 1 1111 tri-state rsync note: initial values are such that all ports are tri-stated.
DS26401DK octal t1/e1/j1 framer design kit 14 of 34 register name: tsync_sr register description: ds26401 tsyncx pin setting register offset: 0x0017, 0x0027, 0x0037, 0x0047, 0x0057, 0x0067, 0x0077, 0x0087 bit # 7 6 5 4 3 2 1 0 name ? ? ? d4 d3 d2 d1 d0 bit 0 to 2: ds26401 port x tsync source (d4, d3, d2, d1, d0) the source for tsync is defined as shown in table 10. table 10. tsyncx source definition d4, d3, d2, d1, d0 tsync connection 00000 tri-state tsync 00001 drive tsync with rsync 1 00010 drive tsync with rsync 2 00011 drive tsync with rsync 3 00100 drive tsync with rsync 4 00101 drive tsync with rsync 5 00110 drive tsync with rsync 6 00111 drive tsync with rsync 7 01000 drive tsync with rsync 8 01010 drive tsync with t1 osc 01011 drive tsync with e1 osc 01100 drive tsync with 16.385mhz 01101 drive tsync with a logic 0 01110 drive tsync with a logic 1 10001 drive tsync with rmsync 1 10010 drive tsync with rmsync 2 10011 drive tsync with rmsync 3 10100 drive tsync with rmsync 4 10101 drive tsync with rmsync 5 10110 drive tsync with rmsync 6 10111 drive tsync with rmsync 7 11000 drive tsync with rmsync 8 11111 tri-state tsync note: initial values are such that all ports are tri-stated.
DS26401DK octal t1/e1/j1 framer design kit maxim/dallas semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a ma xim/dallas semiconductor product. no circuit patent licenses are implied. maxim/dallas semiconductor reserves the right to change the circuitry and specification s without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2003 maxim integrated products printed usa 15 of 34 register name: clk_sr register description: ds21448 mclk a, ds21448 mclk b, and ref clk register offset: 0x0090 bit # 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 table 11. mclk a source definition d1, d0 mclk a (ds21448 ports 1 to 4) 00 tri-state mclk 01 drive mclk with 1.544mhz 10 drive mclk with 2.048mhz 11 tri-state mclk note: initial values are such that mclk is 2.048mhz. table 12. mclk b source definition d3, d2 mclk b (ds21448 ports 5 to 8) 00 tri-state mclk 01 drive mclk with 1.544mhz 10 drive mclk with 2.048mhz 11 tri-state mclk note: initial values are such that that mclk is 2.048mhz. table 13. mclk a source definition d5, d4 ref clk 00 tri-state ref clk 01 drive ref with 1.544mhz 10 drive ref with 2.048mhz 11 tri-state ref clk note: initial values are such that ref is 2.048mhz. ds26401 and ds21448 information for more information about the ds26401 and ds21448, please consult the respective data sheets, available on our website at www.maxim-ic.com/ds26401 and www.maxim-ic.com/ds21448 . technical support for technical support, please email your questions to telecom.support@dalsemi.com . schematics the DS26401DK schematics are featured in the following pages.

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